Regviz

Renesas Electronics /R7FA6M3AH /PTPEDMAC /RMCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RMCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Renesas Electronics/R7FA6M3AH/PTPEDMAC/RMCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)RNR

RNR=0

Description

Receive Method Control Register

Fields

RNR

Receive Request Reset

0 (0): EDRRR.RR bit (receive request bit) is set to 0 when one frame has been received.

1 (1): EDRRR.RR bit (receive request bit) is not set to 0 when one frame has been received.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data